1. Field of the Invention
The present invention relates to a semiconductor memory device and an information processing system including the same. More particularly, the present invention relates to a semiconductor memory device that includes plural core chips and an interface chip to control the core chips and an information processing system including the same.
2. Description of Related Art
A memory capacity that is required in a semiconductor memory device such as a dynamic random access memory (DRAM) has increased every year. In recent years, a memory device that is called a multi-chip package where plural memory chips are laminated is suggested to satisfy the required memory capacity. However, since the memory chip used in the multi-chip package is a common memory chip capable of operating even though the memory chip is a single chip, a so-called front end unit that performs a function of an interface with an external device (for example, memory controller) is included in each memory chip. For this reason, an area for a memory core in each memory chip is restricted to an area obtained by subtracting the area for the front end unit from a total chip area, and it is difficult to greatly increase a memory capacity for each chip (for each memory chip).
In addition, a circuit that constitutes the front end unit is manufactured at the same time as a back end unit including a memory core, regardless of the circuit being a circuit of a logic system. Therefore there has been a further problem that it is difficult to speed up transistors in the front end unit.
As a method to resolve the above problem, a method that integrates the front end unit and the back end unit in individual chips and laminates these chips, thereby constituting one semiconductor memory device, is suggested (for example, Japanese Patent Application Laid-Open (JP-A) No. 2007-157266). According to this method, with respect to plural core chips each of which is integrated with the back end unit without the front end unit, it becomes possible to increase a memory capacity for each chip (for each core chip) because an occupied area assignable for the memory core increases. Meanwhile, with respect to an interface chip that is integrated with the front end unit and is common interface to the plural core chips, it becomes possible to form its circuit with a high-speed transistor because the interface chip can be manufactured using a process different from that of the memory core. In addition, since the plural core chips can be allocated to one interface chip, it becomes possible to provide a semiconductor memory device that has a large memory capacity and a high operation speed as a whole.
However, since there occurs a deviation in operation speed among the core chips due to the manufacturing process conditions, the period of time from the receipt of a read command to the outputting of read data also varies among the core chips. As a result, the latch margin of the read data for the interface chip becomes smaller, and in some cases, read data cannot be accurately latched.
As a method for solving the above problem, FIGS. 11 and 13 of JP-A No. 2006-277870 disclose a method of reproducing a data strobe signal (DQS) that is output from a memory chip and is phase-delayed in an interface chip, and controlling the latch timing of read data on the interface chip with the use of the reproduced data strobe signal in a semiconductor device in which memory chips and the interface chip are stacked, though the semiconductor device is not of a type having a front-end unit and a back-end unit separated from each other. More specifically, as disclosed in paragraphs [0071] through [0073] of JP-A No. 2006-277870, data strobe signals DQS and /DQS supplied from the memory chips at the time of reading generate an internal strobe signal DQSI having a phase 90-degrees shifted from the data strobe signals DQS and /DQS, via each input buffer INB of a differential amplifier type and the strobe signal generating circuit DSG of the interface chip. The latch circuits L of the interface chip capture data DQ supplied from the memory chips, in synchronization with the internal strobe signal DQSI. The data DQ captured in the interface chip and the strobe signals DQS and /DQS are transmitted to the outside. Accordingly, when seen from outside the semiconductor memory device, the overall read latency is obtained by adding one clock that is the latency of the interface chip to the read latency RL of the memory chips, or RL+1.
This relates data latch timing in a semiconductor device having an interface chip added to conventionally known memory chips each operating independently of one another, and has been developed as a solution on the assumption that a delay is caused from the read latency of conventional memory chips as described above.
However, the semiconductor device disclosed in JP-A No. 2006-277870 is not a semiconductor device of a type having a front-end unit and a back-end unit separated from each other, but is a semiconductor device in which conventional memory chips operating independently of one another and an interface chip for relaying data and signals between the conventional memory chips and the outside are stacked. Therefore, the read data that are output from the memory chips are serial-converted data. The read data and the data strobe signals that are output from the memory chips be supplied directly to a controller chip (to the outside) in the case of a regular semiconductor device, and those data and signals are simply buffered by the interface chip. Due to this buffering, extra time is required for supplying read data to the controller chip in practice, and the access speed becomes lower when seen from the controller chip. As described above, the invention disclosed in JP-A No. 2006-277870 fundamentally differs from a semiconductor device of a type having a front-end unit and a back-end unit separated from each other. Therefore, it is difficult for the invention disclosed in JP-A No. 2006-277870 to solve the above described problem.